1. Field of the Invention
The present invention relates to a charge coupled device (CCD) driving circuit. More particularly, the present invention relates to a CCD driving circuit which includes a timing signal generator for generating timing signals used to drive a CCD image sensor, and a synchronizing signal generator integrated on the same chip as the timing signal generator for generating a TV reference signal.
2. Description of the Related Art
It is known that a video camera requires a timing signal generator for generating timing signals used to drive a CCD image sensor. Furthermore, the video camera requires a synchronizing signal generator for generating a TV reference signal. These generators are used to produce timing signals and TV reference signals by dividing clock signals which are input. In order to minimize the size and production costs of the camera, the timing signal generator and the synchronizing signal generator are integrated on the same chip or substrate.
Referring initially to FIG. 3, a known synchronizing signal generator for a CCD driving circuit is shown. The synchronizing signal generator is equipped with a counter that includes D-type flip-flops 31 to 38 disposed in multiple rows with each flip-flop corresponding to a respective row. The Q output of each flip-flop 31 to 38 is connected to its own D-input. In this manner, each D-type flip-flop 31 to 38 forms a frequency divider. The D-type flip-flop 31 in the 1st row receives a clock signal at its CK input, and the D-type flip-flops 32 to 38 in the respective subsequent rows receive the Q output of the immediately preceding D-type flip-flop 31 to 37 at its CK input. As a result, counter outputs Q.sub.1 to Q.sub.8 become half frequency pulses obtained by successively dividing the clock signals provided to each flip-flop from the Q output of the preceding D-type flip-flop. By combining the counter outputs Q.sub.1 to Q.sub.8, a desired TV reference signal is generated as is known.
The timing signal generator (not shown) for the CCD driving circuit is equipped with a counter providing the same type of frequency division. By combining outputs from such a counter, the desired timing signals are generated.
According to the known arrangement described above, the counter in the timing signal generator is kept inoperative while the CCD image sensor is in operation. The counter in the timing signal generator is operative only during a blanking period of time, so that a video signal is protected against noise that may be caused by the operation of the counter.
However, the synchronizing signal generator must be operated during the imaging operation so as to produce TV reference signals. Accordingly, the operation of the counter in the known synchronizing signal generator changes the output logic levels of each D-type flip-flop 31 to 38. As a result, a pulsating current is produced which causes counter noise to occur to the detriment of the video signal. More specifically, as is shown in FIG. 4, when the logic level of one of the counter outputs Q.sub.1 to Q.sub.8 in a particular row is changed, the logic levels of one or more of the other counter outputs Q.sub.1 to Q.sub.8 in the subsequent rows are simultaneously changed. Consequently, pulsating currents generated by such logic level changes overlap one after another, and the resulting counter noise contains components of different divided frequencies. Therefore, even if a clock signal occurs outside the image forming area, a counter noise having a lower frequency component will be mixed in the video signal of the CCD image sensor during the imaging operation due to the timing signal generator which is formed on the same chip. As a result, the video image is spoiled with a solid pattern having vertical strips.
In order to avoid counter noise from occurring in the video image as a result of the synchronizing signal generator, the known CCD driving circuit is configured such that the synchronizing signal generator and the timing signal generator are separated by a source bus and a GND bus. Accordingly, the IC circuit for the CCD driving circuit becomes complicated, and freedom of design is limited.